The 34th Microelectronics Design and Test Symposium

(IEEE MDTS 2025)

 

Date: May 19 – 21, 2025

Location: Albany, New York, USA

Co-sponsors: IEEE Region-1 (Northeastern USA) and IEEE Schenectady Section

 

Call for Papers

Call for Volunteers

Registration

Hotel Reservation

Program

Tutorials

2025 Leadership

  • General Chair: Andrew Laidler, onsemi (alaidler@ieee.org)
  • Vice General Chair: Uma Srinivasan, IBM (umasrin@us.ibm.com)
  • Past General Chair: Kelly Ockunzzi, Marvell Semi (kockunzzi@marvell.com)
  • Program Chair: Tian Xia, University of Vermont (txia@uvm.edu)
  • Vice Program Chairs: Huamin Li, University at Buffalo–SUNY; Marvin Onabajo, Northeastern University
  • Special Session Chairs: Nathaniel Cady, University at Albany–SUNY; Deniz Rende, Rensselaer Polytechnic Institute; Dean Sullivan, University of New Hampshire

Important Announcements

Theme

Advances and Challenges for Chiplets and for Hardware Security

About MDTS 2025

The IEEE Microelectronics Design & Test Symposium (MDTS) provides a forum for academic and industry researchers and engineers to discuss the latest advances in microelectronics, share their visions in modern microelectronic technologies, and foster academic-industry collaboration.

The 34th MDTS explores challenges and advances on two major fronts: chiplets and hardware security. Chiplets break large chip designs into smaller, ideally reusable, blocks, and the Universal Chiplet Interconnect Express (UCIe) standard addresses the challenges of connecting chiplets in the package. Hardware security for chip designs covers a broad range of issues, from preventing reverse engineering to blocking takeovers and data theft or manipulation.

Key Dates

Submission Deadline (abstract and full paper): December 15, 2024
Notification of Acceptance: February 16, 2025
Final Paper Submission: April 13, 2025

Theme Topics

The Program Committee invites researchers and practitioners to submit tutorial, panel, and special session proposals. The committee also encourages authors to submit original, unpublished papers. Topics of interest include, but are not limited to:

Chiplets

  • UCIe interconnect, and packaging
  • Partitioning
  • Design cycle time impact
  • Microprocessor case studies
  • Physical rework in the manufacturing process
  • 2.5D and 3D applications
  • Applications of AI/ML to optimization
  • Heterogeneous integration

Hardware Security

  • Microarchitectural attacks
  • Side channel attacks and mitigation
  • (Anti –)Reverse engineering and physical attacks
  • Fault attacks
  • Hardware obfuscation
  • Computer-aided design (CAD) for security
  • SoC security, Field-programmable gate array (FPGA) and reconfigurable fabric security
  • Internet-of-Things (IoTs) and cyber physical system security

Micro Devices, Circuits and Microsystems

  • Analog/mixed-signal/radio frequency (RF) circuits
  • Low-power low-voltage design
  • Sensors and sensing systems
  • Smart system design for automotive, automation and robotics
  • Circuits and systems for approximate and evolvable computing
  • Memristor-based devices
  • Lab-on-Chip, wearable and implantable devices
  • Heterogeneous integration and multi-scale chiplet-based packaging architecture

Biomedical, Photonics, and Quantum Electronics

  • Biomedical and bio-inspired circuits and systems
  • Microelectromechanical systems (MEMS) sensors and bioelectronics
  • Nanobiophotonics for optical imaging, sensing, and diagnostics
  • Terahertz photonics for communications
  • Photodetectors, sensors, and imaging
  • Photonics for energy and green photonics

Electronic Design & Test Methodologies and Electronic Design Automation (EDA)

  • Electronic design tools, processes and methodologies
  • EDA for 3D integrations and advanced packaging
  • EDA for bio-inspired and neuromorphic systems
  • EDA tools, methodologies and applications for Photonics devices, circuit, and system design
  • System-on-Chip (SoC)/intellectual property (IP) testing strategies
  • Hardware/software co-verification
  • Design for testability (DFT) & built-in self-test (BIST) for digital designs, analog/mixed-signal integrated circuits (ICs), SoCs, and memories
  • Design verification/validation
  • Machine learning datasets for microelectronics design and test

Emerging Technologies and Applications

  • Computing-in-memory architectures
  • Neural networks, AI, ML, and DL in design and test of microelectronics
  • IoT, edge nodes, or pipelines for real-time data visualizations and monitoring in design and test of microelectronics
  • Application of cognitive, neuromorphic and quantum computing
  • High-speed serializer/ deserializer (SerDes)
  • Next-generation design-technology co-optimization
  • Advanced interconnect
  • 3D manufacturing

Paper Submission

TBA

Corporate/University Supporters for MDTS 2025:

2025 Corporate/University Supporter Application Form

Gold-Level: 

 

2024 Corporate/University Supporters:

Platinum-Level:   

Gold-Level:          https://www.cadence.com/

Generosity Grants: and MDTS Alumni