The 34th Microelectronics Design and Test Symposium
(IEEE MDTS 2025)
Date: May 19 – 21, 2025
Location: Albany, New York, USA
Co-sponsors: IEEE Region-1 (Northeastern USA) and IEEE Schenectady Section
Important Announcements
- 11/03/2024: Papers can be submitted through the CMT tool: https://cmt3.research.microsoft.com/MDTS2025/Submission/Index.
- 10/25/2024: TPC has announced the opening of Invited Paper Sessions. Interested authors please contact Program Chair Prof. Tian Xia via email at txia@uvm.edu.
- 09/30/2024: 2025 Corporate/University Supporter Application Form is online.
- 09/21/2024: Call for Papers is online.
- 08/25/2024: Tentative MDTS-2025 information is online.
- Microarchitectural attacks
- Side channel attacks and mitigation
- (Anti –)Reverse engineering and physical attacks
- Fault attacks
- Hardware obfuscation
- Computer-aided design (CAD) for security
- SoC security, Field-programmable gate array (FPGA) and reconfigurable fabric security
- Internet-of-Things (IoTs) and cyber physical system security
- Analog/mixed-signal/radio frequency (RF) circuits
- Low-power low-voltage design
- Sensors and sensing systems
- Smart system design for automotive, automation and robotics
- Circuits and systems for approximate and evolvable computing
- Memristor-based devices
- Lab-on-Chip, wearable and implantable devices
- Heterogeneous integration and multi-scale chiplet-based packaging architecture
- Biomedical and bio-inspired circuits and systems
- Microelectromechanical systems (MEMS) sensors and bioelectronics
- Nanobiophotonics for optical imaging, sensing, and diagnostics
- Terahertz photonics for communications
- Photodetectors, sensors, and imaging
- Photonics for energy and green photonics
- AI/ML integration with biodevices
- Micro/Nano electronics for biosensing and bio-actuation
- Electronic design tools, processes and methodologies
- EDA for 3D integrations and advanced packaging
- EDA for bio-inspired and neuromorphic systems
- EDA tools, methodologies and applications for Photonics devices, circuit, and system design
- System-on-Chip (SoC)/intellectual property (IP) testing strategies
- Hardware/software co-verification
- Design for testability (DFT) & built-in self-test (BIST) for digital designs, analog/mixed-signal integrated circuits (ICs), SoCs, and memories
- Design verification/validation
- Machine learning datasets for microelectronics design and test
- Emerging low-dimensional materials (carbon nanotubes, transition metal dichalcogenides, and metal oxides).
- Computing-in-memory architectures
- Neural networks, AI, ML, and DL in design and test of microelectronics
- IoT, edge nodes, or pipelines for real-time data visualizations and monitoring in design and test of microelectronics
- Application of cognitive, neuromorphic and quantum computing
- High-speed serializer/ deserializer (SerDes)
- Next-generation design-technology co-optimization
- Advanced interconnect
- 3D manufacturing
- Quantum Computing
- Power conversion topologies
- Energy storage systems
- Power electronic packaging
- Electric Vehicles (EV) and charging infrastructure
- Wireless power transfer
Corporate/University Supporters for MDTS 2025:
2025 Corporate/University Supporter Application Form
Gold-Level: 
2024 Corporate/University Supporters:
Platinum-Level: 
Gold-Level: 
Generosity Grants: 
and MDTS Alumni