The 33rd Microelectronics Design and Test Symposium

(IEEE MDTS 2024)

 

Date: May 13 – 15, 2024

Location: Crowne Plaza Albany – The Desmond Hotel, Albany, New York, USA

Co-sponsors: IEEE Region-1 (Northeastern USA) and IEEE Schenectady Section

 

Important Announcements

  • 02/18/2024: Early registration cut-off on April 16th; Group rate for hotel reservation cut-off on April 21st. Please use the reservation link to reserve rooms to help MDTS meet contract requirements.
  • 02/12/2024: The paper submission deadline has been extended to 02/22/2024.
  • 02/05/2024: A note on Hotel Reservation (Link).
  • 01/30/2024: Online registration and hotel room reservation are available now.
  • 11/28/2023: Call-for-Paper is online.
  • 10/17/2023: Tentative MDTS-2024 information is online.

 

Theme

Advances and Challenges for Chiplets and for Hardware Security

About MDTS 2024

The IEEE Microelectronics Design & Test Symposium (MDTS) provides a forum for academic and industry researchers and engineers to discuss the latest advances in microelectronics, share their visions in modern microelectronic technologies, and foster academic-industry collaboration.

The 33rd MDTS explores challenges and advances on two major fronts: chiplets and hardware security. Chiplets break large chip designs into smaller, ideally reusable, blocks, and the Universal Chiplet Interconnect Express (UCIe) standard addresses the challenges of connecting chiplets in the package. Hardware security for chip designs covers a broad range of issues, from preventing reverse engineering to blocking takeovers and data theft or manipulation.

Key Dates

Full Paper or Extended Summary: 02/15/2024 02/22/2024
Notification of Acceptance:             04/01/2024
Final Paper Submission:                    05/01/2024

Theme Topics

The Program Committee invites researchers and practitioners to submit tutorial, panel, and special session proposals. The committee also encourages authors to submit original, unpublished papers. Topics of interest include, but are not limited to:

  • UCIe interconnect, and packaging
  • Partitioning
  • Design cycle time impact
  • Microprocessor case studies
  • Physical rework in the manufacturing process
  • 2.5D and 3D applications
  • Applications of AI/ML to optimization
  • Heterogeneous integration
  • Microarchitectural attacks
  • Side channel attacks and mitigation
  • (Anti –)Reverse engineering and physical attacks
  • Fault attacks
  • Hardware obfuscation
  • Computer-aided design (CAD) for security
  • SoC security, Field-programmable gate array (FPGA) and reconfigurable fabric security
  • Internet-of-Things (IoTs) and cyber physical system security
  • Analog/mixed-signal/radio frequency (RF) circuits
  • Low-power low-voltage design
  • Sensors and sensing systems
  • Smart system design for automotive, automation and robotics
  • Circuits and systems for approximate and evolvable computing
  • Memristor-based devices
  • Lab-on-Chip, wearable and implantable devices
  • Heterogeneous integration and multi-scale chiplet-based packaging architecture
  • Biomedical and bio-inspired circuits and systems
  • Microelectromechanical systems (MEMS) sensors and bioelectronics
  • Nanobiophotonics for optical imaging, sensing, and diagnostics
  • Terahertz photonics for communications
  • Photodetectors, sensors, and imaging
  • Photonics for energy and green photonics
  • Electronic design tools, processes and methodologies
  • EDA for 3D integrations and advanced packaging
  • EDA for bio-inspired and neuromorphic systems
  • EDA tools, methodologies and applications for Photonics devices, circuit, and system design
  • System-on-Chip (SoC)/intellectual property (IP) testing strategies
  • Hardware/software co-verification
  • Design for testability (DFT) & built-in self-test (BIST) for digital designs, analog/mixed-signal integrated circuits (ICs), SoCs, and memories
  • Design verification/validation
  • Machine learning datasets for microelectronics design and test
  • Computing-in-memory architectures
  • Neural networks, AI, ML, and DL in design and test of microelectronics
  • IoT, edge nodes, or pipelines for real-time data visualizations and monitoring in design and test of microelectronics
  • Application of cognitive, neuromorphic and quantum computing
  • High-speed serializer/ deserializer (SerDes)
  • Next-generation design-technology co-optimization
  • Advanced interconnect
  • 3D manufacturing

Paper Submission

Papers can be submitted through the CMT tool: https://cmt3.research.microsoft.com/MDTS2024

Contact Us

For program information, contact: Uma Srinivasan, Program Chair (umasrin@us.ibm.com)

For general information, contact: Kelly Ockunzzi, General Chair (kockunzzi@marvell.com)

Corporate/University Supporters for MDTS 2024:

2024 Corporate/University Supporter Application Form

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Gold-Level:          https://www.cadence.com/

Generosity Grants:

 

Corporate/University Supporters for MDTS 2023:

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Gold-Level:          https://www.cadence.com/

Keynote Sponsor:   

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