The 32nd Microelectronics Design and Test Symposium (MDTS 2023)

Tentative Date: May 8-10, 2023

Location: Albany, New York, USA

Co-sponsors: IEEE Region-1 and Schenectady Section

 

MDTS Call for Volunteers

MDTS is looking for professional practitioners and researchers to join the Program Committee. Please email your principal technical interest and background to us to start a conversation. The effort level of a typical PC member is less than an hour each week (on average) and is to review a maximum of 3 submissions a year. We also encourage PC members to submit their own works. Additional duties and responsibilities are available.

Steering Committee co-Chairs: Xinghao Chen (chenxinghao@ieee.org) and Ted Cooley (escooley03@gmail.com)

Theme

Artificial Intelligence, Machine Learning, and Deep Learning: Tactical and Strategic Impacts to Microelectronics Design and Test

About MDTS 2023

The IEEE Microelectronics Design & Test Symposium (MDTS) provides a forum for academic and industry researchers and engineers to discuss the latest advances in microelectronics, share their visions in modern microelectronic technologies, and foster academic-industry collaboration.  The 32nd MDTS features artificial intelligence (AI), machine learning (ML), and deep learning (DL).  AI/ML/DL algorithms can be used to improve design and test by evaluating the accuracy and effectiveness of models, design rules, and test coverage.  In addition, new circuits and chip architectures for AI/ML/DL applications are emerging, presenting new challenges to design and test in the form of reticle-size die, chiplets, and hardware/software co-design.

Key Dates

Submission Due Date:                  2023/02/26
Acceptance Notification Date:  2023/04/07
Final Paper Submission Date:    2023/04/30

Theme Topics

The Program Committee invites researchers and practitioners to submit proposals for tutorial, panel, and special sessions related to the theme. Topics include:

  • Methods and Procedures for Implementing AI in Design and Test of Microelectronics
  • Extending Design and Test Targets and Limits Using AI
  • Challenges in generating public domain or academic machine learning datasets (specific to Microelectronics) in use to demonstrate AI, ML and DL for the ETL (Extract, Transform and Load) process
  • IOT, edge nodes, or pipelines for real-time data visualizations and monitoring of Microelectronic Design and Test processes and their implications on security
  • Applications of Software Engineering to process and analyze Microelectronics Design and Test data
  • Barriers to deploying AI/ML/DL technologies and methods to Microelectronics Design, Test, and Research practitioners
  • Adopting AI, ML, and DL to manage supply chain and semiconductor test yield challenges
  • Circuit design and test requirements and advancements to support AI applications implemented in hardware: new devices, compute-in-memory, high-speed serdes, etc.
  • Design and test chip architecture challenges for AI applications

Interest Areas

  • Analog/mixed-signal/radio frequency (RF) circuits
  • Low-power low-voltage design
  • Sensors and sensing systems
  • Smart system design for automotive, automation and robotics
  • Circuits and systems for approximate and evolvable computing
  • Memristor-based devices
  • Lab-on-Chip, wearable and implantable devices
  • Heterogeneous integration and multi-scale chiplet-based packaging architecture
  • Biomedical and bio-inspired circuits and systems
  • Microelectromechanical systems (MEMS) sensors and bioelectronics
  • Nanobiophotonics for optical imaging, sensing, and diagnostics
  • Terahertz photonics for communications
  • Photodetectors, sensors, and imaging
  • Photonics for energy and green photonics
  • Electronic design tools, processes and methodologies
  • EDA for 3D integrations and advanced packaging
  • EDA for bio-inspired and neuromorphic systems
  • EDA tools, methodologies and applications for Photonics devices, circuit, and system design
  • System-on-Chip (SoC)/intellectual property (IP) testing strategies
  • Hardware/software co-verification
  • Design for testability (DFT) & built-in self-test (BIST) for digital designs, analog/mixed-signal integrated circuits (ICs), SoCs, and memories
  • Design verification/validation
  • Machine learning datasets for microelectronics design and test
  • Microarchitectural attacks
  • Side channel attacks and mitigation
  • (Anti –)Reverse engineering and physical attacks
  • Hardware obfuscation
  • Computer-aided design (CAD) for security
  • SoC security, Field-programmable gate array (FPGA) and reconfigurable fabric security
  • Internet-of-Things (IoTs) and cyber physical system security
  • Computing-in-memory architectures
  • Neural networks, AI, ML, and DL in design and test of microelectronics
  • IoT, edge nodes, or pipelines for real-time data visualizations and monitoring in design and test of microelectronics
  • Application of cognitive, neuromorphic and quantum computing
  • High-speed serializer/ deserializer (SerDes)
  • Next-generation design-technology co-optimization
  • Advanced interconnect
  • 3D manufacturing

Paper Submission

Papers can be submitted through the CMT tool: https://cmt3.research.microsoft.com/IEEEMDTS2023/ (Authors will first need to register for a Microsoft CMT account before submitting the paper)

Contact Us

For program information, contact: Uma Srinivasan, Program Chair (umasrin@us.ibm.com)

For general information, contact: Kelly Ockunzzi, General Chair (kockunzzi@marvell.com)

Corporate Supporters for MDTS 2023 (So Far):

MDTS 2023 Supporter Application

Diamond-Level:   

Gold-Level:         

Corporate Supporters for MDTS 2022:

Diamond-Level:          

Platinum-Level: 

Gold-Level:          https://www.cadence.com/